The invention pertains to circuits for communicating signals between integrated circuits. More specifically, the invention pertains to circuitry for communicating signals between integrated circuits in such a manner that the pin count of the integrated circuits and the number of interconnections required between integrated circuits to be interconnected are reduced.
It is known in the prior art that the number of pins needed per integrated circuit and the number of interconnections between integrated circuits can be reduced by utilizing multi-level signals instead of binary signals. In such systems, a digital signal composed of two bits, for instance, is encoded to four levels. That is, four separate and distinct voltage levels are employed on the output and input pins of the transmitting and receiving integrated circuits to represent corresponding digital values of 00, 01, 10, 11.
IBM Technical Disclosure Bulletin, Vol. 18, No. 9, February 1976, describes a multi-level bi-directional signal transmission scheme in which a digital signal is encoded and transmitted from one circuit to another using multiple current levels. In the receiving circuit described in the Technical Disclosure Bulletin, the received signal is applied to first comparison inputs of three comparator circuits, for the case of a ternary-encoded transmitted signal. The state of the signal can be detected from the outputs of the three comparators. Although some pin count and wiring reduction can be achieved with this scheme, nevertheless, the arrangement described suffers from difficulties including the necessity for tight power supply regulation, high power dissipation and circuit complexity.
U.S. Pat. No. 3,484,559 to Rigby discloses a system for communicating digital information, for instance, a dialed number, through a telephone line. The transmitting end circuitry includes a conversion device in which each item of information to be transmitted is converted into a unique combination of a number of discrete current or voltage levels. At the receiving end, the received signal is compared with a set of fixed levels to decode the digit being transmitted. FIG. 2 of that patent is an example of the transmitting end circuitry. Although perhaps suitable for transmitting digital information through a telephone exchange, the arrangement of Rigby has a number of drawbacks which make it unsuitable for use in transmitting signals between integrated circuits. First, large numbers of Zener diodes are required. It is difficult to fabricate a Zener diode in an integrated circuit with high accuracy. Secondly, high power supply voltages are required (+12 V and -50 V). Such voltages are not available in most computer or other digital processing circuitry.
Fink and Fink et al. in U.S. Pat. Nos. 3,702,473 and 3,702,474 describe a technique for monitoring information from a plurality of remote stations. At each remote station, one of seven possible resistances is connected across a transmission line. In a central station, the resistance on the transmission line is sensed to provide an indication of the resistance value connected at the remote station. Such an arrangement also is not suitable for use in transmitting signals between integrated circuits due to the complex circuitry required and the large number of resistances which must be fabricated with great accuracy.
In a patent to Proebsting, U.S. Pat. No. 3,832,576, a combination field-effect/bipolar circuit is provided to encode and transmit information from one integrated circuit to another. The input to the encoder circuit is coupled to both the gate of a field-effect transistor and the emitter of a bipolar transistor, with the outputs of the two transistors gated to provide three distinct signal levels on the output pin. This circuit is unsuitable for many integrated circuit applications in that both positive and negative supply voltages are required. Also, the impedance on the output pin changes considerably between signal levels, thereby leading to the possibility of undershoot, overshoot or ringing on the interconnecting transmission line.
The U.S. Pat. No. 4,031,477 to Shaw teaches a system for transferring logic signals between two locations in which a receiving side circuit, composed of a Zener diode and a resistor network, sets one of four voltage levels on a transmission conductor. At the receiving side, another Zener diode and resistor network converts the signal on the transmission conductor into two ternary signals which are applied to dual-threshold CMOS logic gates which activate one of four binary output signals corresponding to the signal being transmitted. This circuit is not suitable for use in transmitting signals between integrated circuits, again because of the necessity of providing Zener diodes and the requirement of resistors having accurately controlled resistance values.
Ohashi et al. in U.S. Pat. No. 4,070,650 teach a digital signal transmission system for transmitting, for instance, switch settings from a remote location to receiving and utilization circuitry through a single signal line. With reference to FIG. 5 of the drawings of that patent, a timing pulse generating circuit 6 applies pulses in sequence through resistors R11-R14 to base inputs of switching transistors Tr6-Tr9 in an encoder section E. The resistances of collector-circuit resistors R15-R17 are precisely set so that a voltage applied on line 11 is precisely determined by the value of the resistors R15-R17 and which of the switches SW1-SW4 is closed when the corresponding switching transistor Tr6-Tr9 is activated by a pulse from the timing pulse generating circuit 6. In the receiving side decoder section D, a level discriminating circuit 8 is provided which includes comparators OP1-OP4 to which the transmitted signal on the line 11 is applied. A voltage dividing network composed of resistors R19-R23 provides comparison voltages for the comparators OP1-OP4. The outputs of the comparators OP1-OP4 are coupled through diodes D7-D10 to respective inputs of a holding output circuit 9. The comparators OP1-OP4 are further connected in a cascade arrangement through a diode network composed of diodes D1-D6. In this circuit, the comparator having a set comparison value nearest to the signal value on the line 11 is activated, and the outputs from the other comparators are suspended through the cascade connections provided through the diodes D1-D6. This circuit arrangement 2 is unsuitable for use in communicating signals between integrated circuits for a number of reasons. First, the circuitry described by Ohashi et al. is quite complex and would require a large amount of chip area in order to implement. Further, as in many of the cases discussed above, precisely controlled resistance values are required.
In U.S. Pat. No. 4,100,429 to Adachi there is described a FET logic circuit in which a three-level input signal is transmitted and decoded into binary signals. As indicated in FIG. 1 of the drawings of this patent, the signal to be transmitted on a line E can have one of three states: V.sub.DD, ground and open. A clock circuit composed of FET transistors M.sub.1 and M.sub.2 is also connected to the line E. When the input signal is at the V.sub.DD level, the voltage on the line E will also be at that level. Similarly, when the input signal is at ground, the signal on the line E will be at the ground level, independent of clocking signals applied through the FETs, M.sub.1 and M.sub.2. In the open state of the input signal, and only in that state, clock pulses are applied to the line E through the FETs M.sub.1 and M.sub.2. At the receiving end, a circuit is provided which can discriminate among levels of V.sub.DD, ground and the pulsed state (corresponding to the input signal being in the "open" state). It is to be noted that this circuit is suitable only for three-level signals. Also, due to the necessity of detecting the pulsed state, a considerable delay is encountered from the time that the receiving circuitry is activated until it is known for certain what the state of the transmitted signal is.
Yamaguchi, in U.S. Pat. No. 4,115,706, teaches an arrangement very similar to that of the above-discussed Adachi patent in which an input signal can have only one of three possible states, "1", "float" and "0" levels. Only the implementation of the basic scheme is different.
Mayumi in U.S. Pat. No. 4,267,463 teaches a digital integrated circuit in which input/output terminals are also used as control terminals to save pin count for the integrated circuit. In a normal logical voltage range (-0.5 to +5.5 V in the case of TTL) the input/output terminals function as normal input/output terminals, but at a higher voltage region (for instance, +8 V for TTL), they function as control terminals. A special inverter (reference numeral 21) having a high threshold value is employed to sense when the corresponding input/output terminal is above the normal logic range and to switch the operating mode in response thereto. Although this circuit may be useful in some applications, nevertheless, it is not capable of transmitting multi-level signals, each level of which corresponds to a different binary output. Hence, the usefulness in reducing pin count in a more general context in which it is not always possible to share an input/output terminal between data and control uses is limited.
Accordingly, it is an object of the present invention to provide circuitry for transmitting data signals between integrated circuits in which the pin count for each circuit, at both transmitting and receiving ends, is reduced.
It is a further object of the present invention to provide such circuitry which requires very little chip area and which is simple to implement in integrated circuit form.
It is the yet further object of the present invention to provide such circuitry in which only a small amount of power is consumed and ground shift problems between circuits are not present.
Still further, it is an object of the invention to provide such circuitry in which no Zener diodes are required and which does not require the provision of resistors having precisely controlled resistance values.